AVERAGE MODELING Average models are versatile design companions

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Average models are available for many years to power supply designers using SPICE as a simulation engine. Considering the absence of switching component in the models, they simulate fast and are extremely useful to analyze dc-dc converters in the low- or high-voltage arena. Based on a set of nonlinear expressions, these models are linearized by SPICE around a dc operating point, making the models capable of predicting the small-signal response of a given converter such as a buck or a buck-boost type for example.

It is however less known that these models can be efficiently used in more complex environments such as three-phase power factor correction (PFC) in which they excel in simulation speed but also in ac analyses, crucial for stabilizing loops. This article will describe what average modeling implies and how designers can apply this concept for stabilizing PFC circuits.

Average modeling with state-space averaging

When analyzing the ac response of a switching converter, you need to describe the operating waveforms with time-continuous equations. One option is to resort to the state-space averaging technique (SSA) introduced in 1976 by Dr. Ćuk [1]. This technique requires the manipulation of matrixes describing the converter’s state variables for the two or three operational modes the circuit crosses while operating. A smoothing process is then applied to build a set of nonlinear but time-continuous expressions, later linearized to build an equivalent electrical model. With this linear model in hand, the designer can apply the Laplace transform and extract the transfer functions of his choice. One major drawback, in my opinion, lies in the fact that SSA considers the entire converter for modeling purposes. Should you want to add a parasitic term in the circuit to check its effect on the ac response, you would need to restart the analysis from scratch.

When the switch turns on, the input source biases the RLC network through the transistor’s r_DS(on). When the main power switch is off, the same RLC network is involved, this time with the freewheel diode conducting. As explained in the previous lines, you need a link between these two distinct states for describing the circuit along a complete switching period. Unfortunately, a singularity occurs during the switch transitions from the on-to-off state and vice versa. The SSA provides a convenient way to smooth this discontinuity by observing that each linear network is active during DT_SW (on-time) or (1-D)T_SW for the off-time. By providing weight to each network during its active period of time, you naturally link the events and obtain a time-continuous nonlinear equation:

In this expression, x represents the state variable (x₁ for the inductor current and x₂ for the capacitor voltage) and u is the dc source. A and B are the state coefficient matrixes, respectively for the on- and off-states. This nonlinear expression now needs to be linearized and translated into an equivalent linear network from which you will extract the transfer function you want, e.g. control-to-output or output impedance.

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The PWM switch model

In 1986, Dr. Vatché Vorpérian came up with the idea of the PWM switch model [2]: considering that linear networks were involved during the static on- or off-states of power switches, why not concentrate the linearization efforts on the switching cell alone, the real culprit for producing time-discontinuous waveforms? This is the philosophy already adopted with the familiar hybrid-π model describing the small-signal model of a bipolar transistor: a set of equations links the three connecting terminals – base, collector and emitter – independently from the environment where the transistor is connected. For analyzing a circuit involving one or several bipolar transistors, simply remove the transistor symbols and replace them with the hybrid-π model, respecting the connecting ports. Figure 2 illustrates this well-known technique:

The term invariant equally applies to the bipolar and the PWM switch models, meaning that internal equations do not change, whatever the electrical configuration. For instance, the hybrid-π model could be used in a common-collector or common-base configuration, its internals won’t vary and you don’t have to tweak the model based on the electrical diagram you are dealing with. Same goes for a switching converter in which the PWM switch will take place. Whether the PWM switch model is plugged in a buck, a flyback or a SEPIC, the expressions linking the three terminals (a for active, p for passive and c for common) remain identical. It is truly one of the strengths of this approach compared to SSA. It means that if, later, you want to add a front-end filter or include more ohmic losses in the switching paths, the model does not change, just update the electrical diagram.

Figure 3 shows how this equivalent invariant large-signal model of the switching cell is inserted in place of the original circuit involving the switch and the diode. The switching cell is now described by a time-continuous network which can be simulated by SPICE in a .AC analysis. The solver will linearize the circuit around a dc operating point and delivers the ac response the designer wants to plot. In the original switching circuit, a naturally-sampled pulse-width modulator (PWM) generates the driving waveform to actuate the power switch on and off. The toggling event occurs when the artificial sawtooth intersects with the control dc voltage. With a value of 851 mV and a peak sawtooth voltage of 2 V, the corresponding duty ratio will be 0.851/2 = 425 mV or 42.5% considering a 1-V full scale for the D input of the PWM switch model. To model this block, a simple gain of 1/V_p will do and it is the 0.5 gain you see in the average model.

For studying most of the classical circuits, the implementation of the PWM switch is straightforward. That is what I have represented in Figure 4. Sometimes, you need to reveal the common connection of the switch and diode by transforming the circuit. It is the case for the SEPIC or the Ćuk converter for instance. Isolated topologies such as the flyback or the forward can also be easily modeled by adding a perfect transformer. Additional details about deriving and implementing the PWM switch will be found in reference [3].

We now have a look at how to implement this approach in three-phase power factor correction circuits (PFCs).

Three-phase PFC simulations

In this short article, we cannot review all the topologies suitable for building three-phase PFCs. We will concentrate the analysis on a 6-pack version, a popular structure which is naturally bi-directional. Figure 5 shows a possibility to control it with a dq0 algorithm. In a nutshell, this technique synthetizes the three rotating input current vectors into one single space vector via the Clarke transformation. This vector is then processed by the Park transformation to become two dc components, d (direct) and q (quadrature), respectively representing the active and reactive power (in a PFC application). A regulation loop adjusts these components to ensure a sinusoidal current absorption with a regulated output voltage. q is often set to zero (for a near-unity power factor) but not always as some applications require the circulation of reactive current.

A second inverse-transform block builds the three new current setpoints from the dc-controlled d and q variables (i_d and i_q in Figure 5) and drives the six transistors via dedicated modulators and drivers.

As with any closed-loop system, stability analysis must be carried over the three loops, with different compensation goals. For example, unlike with single-phase PFCs, the crossover frequency of the voltage regulation loop can be pushed up to 100 Hz as there is no low-frequency ripple on the output capacitor. For the d and q loops, crossover frequencies of a few kHz are usually well suited for a digital control system.

The control-to-output transfer function of these three loops can be obtained in different manners, including mathematical analysis and simulation with an averaged model as documented in Ref. [4]. In this paper, authors identify the PWM switch as a potential candidate to model a three-phase PFC but without presenting a simulation diagram. It is what I propose in Figure 6 with three PWM switch models in action. The input currents are sensed via three H sources, scaling the reading by a 80-mΩ ratio. These voltage images will feed the dq0 transform block which, together with the Θ angle extracted from the input voltages, delivers the instantaneous dc values for the d and q variables. Type 2 compensators then individually shape the ac responses of the three loops and confirm the good compensation strategy as shown in the right side of the figure.

In parallel with the average model simulations, I have built a cycle-by-cycle switching circuit made of perfect switches for speeding the simulation up (Figure 7). Once all is working as expected, you can improve the schematic by modeling the drivers and inserting SiC MOSFET models (or IGBTs). Before upgrading a working circuit with imported models, I recommend you validate them via a double-pulse test as described in Ref. [5]. This test is important if you don’t want to waste time with long simulations finally leading to wrong results.

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Now that our circuit has been stabilized, we can run a transient test and verify the corresponding waveforms. In this 400-V converter supplied from three 120-V ac sources (three-phase 208-V network), the output power is stepped from 5 to 10 kW with a few amperes per microsecond slope. The left side of Figure 8 depicts results delivered by the averaged models in a few seconds. The input signals are well sinusoidal and the drop of the output voltage remains below 20 V, with a clean recovery, without noticeable overshoot. The transient responses of the d and q loops are also extremely stable, confirming the adopted compensation strategy. The right side of the figure shows the same waveforms but, this time, obtained with the switching circuit. If we could superimpose the curves in LTspice, the averaged values would exactly match the switching waveforms. This confirms the excellent correspondence between the models and the cycle-by-cycle circuit. So not only you can trust the ac response, but you can also carry many different tests on the averaged circuit, being confident that it will faithfully reproduce what the switching circuit would do, but with at the expense of a longer simulation time.

Beside drastically reducing the simulation time, an average model lets you run many different tests like Monte Carlo or extreme value analysis (EVA) to test how component tolerances affect the stability or the total harmonic distortion (THD) as possible usage examples.

These PFC simulation examples, as well as many more, can be freely obtained by downloading my ZIP file through the link provided in Ref. [6].

Conclusion

This article has described how to use average models for simulating the complex architecture of a 6-pack three-phase power factor correction circuit. These models are useful for studying the small-signal response of the multiple loops found in this complicated converter. Once the dynamic response is obtained, the designer can select an adequate compensation strategy and immediately check the results on a transient response to a load step. The comparison between average modeling and a switching circuit confirms the validity of the approach.

References

• 1. S. Ćuk, Modelling Analysis, and Design of Switching Converters, Ph. D. dissertation Caltech, 1976

• 2. V. Vorpérian, Simplified Analysis of PWM Converters using Model of PWM Switch, parts I and II, IEEE Transactions on Aerospace and Electronic Systems, Vol. 26, NO. 3, 1990

• 3. C. Basso, Switch-Mode Power Supplies, Second Edition: SPICE Simulations and Practical Designs, McGraw-Hill, 2014

• 4. H. Mao, D. Boroyevich, F. Lee, Novel Reduced-Order Small-Signal Model of a Three-Phase PWM Rectifier and Its Application in Control Design and System Analysis, IEEE Transactions on Power Electronic, Vol. 13, NO. 3, 1998

• 5. C. Basso, Double-Pulse Test helps validating SiC SPICE models, PCIM News Platform, February 2025

• 6. C. Basso, Summer 2025 LTspice files collection, released in July 2025 from the author webpage

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