SIC MODULES Beyond wire bonds: The advanced packaging revolution inside power modules

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ROHM Semiconductor GmbH

Rogers Corporation

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Packaging materials account for roughly a third of a power module's cost, and in modern SiC modules, they increasingly set its lifetime too. A silver-sintered die attach survives around 22 times more power cycles than a soldered one in Infineon's published testing, a silicon nitride AMB substrate withstands 5,000 thermal shock cycles where standard alumina DBC fails at 55, and embedding the die in the substrate cuts commutation loop inductance from tens of nanohenries to roughly one.

With SiC and GaN dies now switching at slew rates their packages were never designed for, the solder joints and aluminum wires that defined power modules for four decades are being replaced, layer by layer.

Die attach, from solder to sintering

A standard SAC solder joint melts at 217 to 220°C and conducts heat at under 65 W/mK, which leaves little margin in a module whose SiC die is rated for 175°C junction operation and could physically tolerate more. Under repeated power cycling, the joint's grain structure coarsens, voids form and link into cracks, and thermal resistance climbs until the die overheats. Sintered silver replaces the joint with a porous metal layer formed below 250°C that then behaves like bulk silver, melting at 961°C, conducting at 150 to 250 W/mK, and coming out roughly 70% thinner than a solder bond line, per Semikron Danfoss, which has run silver sintering in mass-produced modules since 2007.

Infineon's .XT interconnect technology, which pairs sintered die attach with copper wire bonds, logs around 225,000 power cycles at a 175°C maximum junction temperature and 2-second on-time, against around 10,000 for the standard soldered and aluminum-bonded stack, and keeps working at 200°C, where the older construction can't operate without severe derating. Heraeus Electronics claims up to 10 times the power cycling lifetime for its pressure-sintered silver pastes, and a more conservative four times module lifetime for a fully sintered module versus a fully soldered one. Sintered layers also cut peak die temperature by more than 10°C in the company's testing, and every 10-degree reduction roughly doubles die lifetime.

Silver's cost keeps the pressure on for an alternative, and copper sinter pastes are the leading candidate: copper runs around 100 times cheaper than silver as a raw material, but oxidizes readily and needs a protective atmosphere through drying, placement, and sintering, so the process ecosystem is still maturing. Equipment makers are moving first. ASMPT's SilverSAM PRO sinter press platform, shown at PCIM Europe 2026 in Nuremberg in June, ships with an oxidation-free process chamber designed explicitly for copper-compatible sintering on DBC and AMB panels.

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Interconnect, from wire bonds to clips and embedded die

A single 500-micron aluminum bond wire fuses at about 35 A, so high-current modules parallel dozens of them, and every one is a fatigue site. Aluminum expands at around 23 ppm per degree Celsius, against silicon's 3, and each thermal cycle flexes the bond heel until it cracks or the foot lifts off the die. Aluminum ribbon raised the ceiling, with a 2,000 by 300-micron ribbon carrying around 105 A in place of three heavy wires, but the geometry and the fatigue mechanism stay the same.

Copper clips remove the wire entirely, replacing it with a stamped plate soldered or sintered across the die's top surface. Danfoss's Bond Buffer process shows what the copper transition is worth even in wire form: a sintered copper buffer on the die enables copper wires with a bonded cross-section more than 20 times larger than conventional wiring, a 9% cut in thermal resistance, and a 100 mV lower forward voltage drop at 200 A. The approach has automotive precedent at scale, since the Tesla Model 3's inverter used 24 molded STMicroelectronics SiC modules with copper ribbon connections rather than aluminum wire as far back as 2018.

Embedded die goes further and eliminates the loop itself, and the math behind it is unforgiving. At 10 A/ns, every 10 nH of loop inductance adds 100V of overshoot on top of the bus voltage. A discrete TO-247 contributes 5 to 7 nH of package inductance before the PCB loop is counted, while Infineon's embedded 1,200V CoolSiC S-cell measures around 2 nH, and its p2PACK program with Schweizer Electronic has run 1,200V, 11 mΩ embedded SiC in a 50 kW evaluation at 900V input.

Fraunhofer IZM and Mitsubishi Heavy Industries published a 500 kW-per-liter SiC inverter in June 2026, built on AMB chip embedding, with six paralleled 1,200V dies per switch, a primary commutation loop of about 1 nH, 65 V/ns slew rates, and better than 99% efficiency at 500 ARMS. At PCIM Europe 2026, ASE subsidiary USI showed SiC die embedded in multilayer ABF substrates targeting 400V and 800V EV inverters and AI data center power, a sign of how much OSAT interest the format is drawing.

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Substrates and double-sided cooling

The ceramic under the die faces the same escalation. Standard 96% alumina DBC conducts at 24 W/mK and survives around 55 thermal shock cycles between -55 and 150°C before the copper delaminates; aluminum nitride DBC conducts far better at 180 W/mK but is brittle, with the lowest fracture toughness of the common ceramics, and fails the same test at around 35 cycles.

Silicon nitride brazed under an active metal braze (AMB) process conducts at 90 W/mK, carries roughly double the flexural strength of either alternative, and passes 5,000 cycles of the same test. Fracture toughness, not bending strength, turns out to be the property that predicts substrate life, and Si3N4's 6.5 to 7 MPa·m0.5 is roughly double AlN's. Thicker copper for higher current density is a side benefit of the braze, and it's why Si3N4 AMB has become the default under high-power SiC.

Substrate suppliers are scaling in response, with Rogers expanding curamik AMB capacity into China after enlarging its German plant, and research programs such as the PVA TePla and Fraunhofer IISB joint lab working on aluminum nitride crystal growth for the next substrate generation.

Yole values power module packaging raw materials at $4.1 billion by 2028, around 28% of total module value, growing at 11% annually through 2030 per its latest packaging report. Wolfspeed's 2025 YM six-pack, with sintered die attach and copper clip interconnects, claims three times the power cycling capability of its predecessor, and Infineon's CoolSiC G2 EasyPACK modules running .XT interconnect at 175°C with 200-degree overload capability shows where volume production is.

The SiC or GaN die in a well-designed 2026 module is no longer the component that wears out first, and keeping it that way is now the packaging engineer's problem.

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