POWER CONVERSION The battle for every nano-watt: Challenges in designing ultra-low-power converters

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For decades, power electronics focused on maximizing kilowatt throughput for industrial grids and electric drivetrains. Today, a quiet revolution operates at the opposite end of the spectrum, where the defining engineering challenge is managing ambient power inputs that are barely detectable. As trillions of edge-nodes deploy globally, the requirement for complete energy autonomy has turned efficient power management into the ultimate system bottleneck.

This operational shift has made traditional battery dependencies obsolete, forcing reliance on ambient thermal gradients, indoor light, and stray radio frequencies. However, these environmental sources do not provide steady electrical rails; they deliver intermittent, sub-optimal voltage levels that sit well below the threshold of standard silicon. Consequently, managing this scarce energy requires power conversion architectures that can operate where the line between active power delivery and background noise is almost non-existent.

The relentless expansion of the Internet of Things (IoT), wearable medical devices, and structural health monitoring has pushed energy harvesting to its absolute

physical limits. When operating on microwatts of harvested environmental energy, the power converter is no longer just a voltage regulator; it is the primary gatekeeper of system viability. Designing at this scale requires a paradigm shift where traditional loss mechanisms are re-evaluated, and every single nano-watt must be fiercely defended.

The architecture of scarcity: buck vs. boost for sub-volt inputs

At sub-volt inputs (10–100 mV), choosing between Buck and Boost topologies defines the system's survival. The Boost converter is essential for ultra-low voltage sources like thermoelectric generators, but it faces the "cold-start paradox": it lacks the voltage to turn on its own transistors, requiring high-overhead auxiliary startup circuits. Conversely, the Buck converter avoids this initialization crisis because it operates from a pre-charged higher-voltage buffer, though it requires the input rail to be established first.

The internal loss mechanisms of each architecture further dictate nano-watt efficiency. The Boost converter suffers from continuous conduction losses and high peak currents, which increase inductor copper losses and require large, leaky components. The Buck topology delivers a smoother output current with lower ripple, reducing capacitor size and leakage. However, its pulsed input current can easily collapse weak, high-impedance harvesting sources if input decoupling is inadequate.

Ultimately, the choice depends on the harvesting source's impedance and voltage profile. The Boost converter remains the mandatory gatekeeper for extracting power from the absolute lowest ambient voltages despite its startup penalties. Meanwhile, the Buck architecture is the superior choice for conserving and regulating energy once a stable voltage pool exists, offering minimized switching losses and lower quiescent current.

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Minimizing quiescent current below 100 nA

The quiescent current (IQ) represents the baseline consumption of the power converter when it is active but delivering zero load current. In nano-watt energy harvesting systems, where the device spends over 99% of its operational life in sleep or standby modes, IQ is the primary determinant of battery longevity and system viability. Reducing this parameter below the 100 nA threshold demands a total departure from continuous-time analog architectures. Traditional error amplifiers, reference generators, and comparators must be replaced by event-driven or heavily duty-cycled topologies that execute control decisions in discrete, sub-nanosecond time windows, suppressing static bias currents to near-zero levels.

Achieving sub-100 nA performance requires a fundamental redesign of the internal voltage references, migrating from conventional, power-hungry Bandgap circuits to sub-threshold sub-1V references. These circuits bias internal MOSFETs strictly within their weak inversion region, where conduction currents naturally scale down to the pico-ampere range. To safeguard the regulation loop against the heightened thermal noise and process-voltage-temperature (PVT) variations inherent to sub-threshold operation, high-impedance passive filtering and digital self-calibration routines are implemented. These routines execute exclusively during the system boot sequence, avoiding ongoing energy penalties during steady-state regulation.

The final frontier in setting IQ below 100 nA is the mitigation of sub-threshold and gate oxide leakage currents within the silicon substrate itself. Designers must utilize Silicon-on-Insulator (SOI) processes or implement transistor stacking (cascoding) techniques to distribute voltage stress across multiple gates, which exponentially decreases drain-induced barrier lowering (DIBL) leakages. Furthermore, the digital control logic must be synthesized using specialized long-channel FET cells. This intentionally trades off switching speed—which is non-critical at these frequencies—to eliminate static leakage power dissipation across the entire chip.

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Cold-start techniques: initializing sub-volt regimes from empty energy pools

The cold-start sequence represents the most critical operational phase of an energy-harvesting power converter, occurring when the storage element (supercapacitor or battery) is fully depleted and the system memory is entirely empty. At this baseline state, the core control loop faces a deterministic deadlock: it requires a stable voltage rail to bias its internal driving circuitry, yet it cannot establish that rail because the ambient transducers (such as thermoelectric generators or indoor photovoltaic cells) deliver sub-volt inputs (10–100 mV) well below the threshold voltage (Vth) of standard silicon. To break this startup paradox, the architecture must bypass the main high-efficiency regulator during initialization and rely on a dedicated, ultra-low-overhead auxiliary cold-start fluidic circuit that can operate purely on the raw, unregulated environmental input.

To achieve initialization from low-voltage inputs without relying on external bias rails, sub-volt cold-start mechanisms commonly deploy either mechanical-electrical resonators or native, zero-threshold MOSFETs (V_th≅ Ø V) arranged in highly sensitive oscillator configurations. Meissner-based oscillators using discrete transformers or low-power ring oscillators drive charge pumps that step up the millivolt-level input via charge-transfer switches operating in their sub-threshold regimes. This auxiliary path does not aim for power conversion efficiency; its sole purpose is to accumulate charges into a secondary, high-impedance startup capacitor, slowly raising its voltage node until it crosses the minimum operational threshold required to wake up the main internal Bandgap reference and the digital control state machine.

The transition from the auxiliary cold-start circuit to the primary high-efficiency regulation loop demands a strict, glitch-free handoff protocol to prevent system reset. An internal, nano-power voltage supervisor constantly monitors the auxiliary startup node; once this node reaches the critical wake-up potential, the supervisor triggers a hardware level-shifter that deactivates the high-overhead startup oscillator and routes the transducer output directly to the main Buck or Boost stage. Simultaneously, the initial boot sequence of the empty digital control logic executes under hardware-default registers, preventing unpredictable gate-drive states or excessive inrush currents that could prematurely collapse the fragile, newly established voltage pool.

The role of inductors and capacitors in minimal form factors

In ultra-low-power (ULP) conversion, scaling down the physical volume of passives is not merely a constraint of wearable ergonomics; it is a direct compromise with the system's energy efficiency. For energy-harvesting nodes operating with sub-100 nA quiescent currents, the parasitic behaviors of inductors and capacitors often supersede their nominal values. In extremely constrained form factors, designers cannot rely on bulky passives to smooth out ripples or store large energy reserves. Instead, every micro-henry and micro-farad must be optimized alongside their intrinsic non-idealities, as the power loss originating from component leakage or core dissipation can easily surpass the active power delivered to the load.

Capacitor selection in ULP architectures represents a delicate balance between energy density and leakage current (I_leak). While high-capacitance multi-layer ceramic capacitors (MLCCs) or small-profile supercapacitors offer the necessary volume to buffer energy during intermittent harvesting cycles, their material composition introduces severe insulation resistance degradation. Standard high-permittivity ceramics (such as Y5V or X7R) can exhibit leakage currents in the micro-ampere range when subjected to voltage stress, which would immediately collapse a nano-watt power budget. Consequently, minimal form-factor ULP systems must deploy ultra-stable, tight-tolerance Class 1 dielectric ceramics (like C0G/NP0) or specialized low-leakage tantalum-polymer capacitors, prioritizing sub-nano-ampere static isolation over raw volumetric efficiency.

On the magnetic front, shrinking the physical size of the inductor to fit micro-form factors forces a steep escalation in both Direct Current Resistance (DCR) and core losses. A smaller inductor footprint requires thinner wire gauges, which drastically increases the copper winding losses (I² . DCR) during high-peak-current bursts, such as those encountered in Pulse Frequency Modulation (PFM) or Boost topologies. Furthermore, miniaturized power inductors exhibit lower magnetic saturation currents (I_sat), increasing the risk of core saturation during transient events, which causes a sharp drop in effective inductance and sparks catastrophic efficiency

losses. Designers must therefore co-optimize the switching frequency with the magnetic core material, selecting ultra-thin, high-permeability composite cores that suppress AC core losses and eddy currents without bloating the physical Z-height of the system.

Conclusions

The design of ultra-low-power (ULP) power converters for energy harvesting systems represents a fundamental departure from traditional analog design methodologies. The transition to an operational regime governed by nano-watts shifts the engineering focus away from raw power throughput toward the strict mitigation of parasitic leakages and standby inefficiencies.

Throughout this paper, it has been demonstrated that:

• Topology: The selection between Buck and Boost architectures extends beyond simple voltage conversion; it defines the critical management of the environmental transducer's impedance profile and the compromise with cold-start penalties.

• Quiescent Current (IQ): Driving the quiescent current below the 100 nA threshold demands a migration toward sub-threshold (sub-1V) voltage references and the use of transistor stacking (cascoding) or SOI processes to suppress silicon substrate leakages.

• Zero-Energy Initialization: The cold-start paradox with sub-volt inputs (10–100 mV) is effectively resolved through self-oscillating auxiliary circuits (via resonators or native zero-threshold MOSFETs), requiring strictly controlled handoff protocols to prevent node collapse.

• Passive Components: In minimal form factors, the non-idealities of passives dominate the energy budget. This makes it mandatory to sacrifice volumetric density in favor of sub-nano-ampere static isolation by utilizing Class 1 ceramics (C0G/NP0) or high-permeability composite magnetic cores.

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Future work

To establish the long-term viability of next-generation autonomous IoT nodes and implantable medical devices, future research avenues should focus on the following key areas:

• Hybrid and Dynamic Regulation Architectures: Develop converters capable of autonomously switching between Buck and Boost topologies in real time, adapting to ambient source fluctuations and the state of charge of the intermediate storage element.

• Integrated Silicon-Passive Co-Design Systems: Investigate the viability of on-chip integrated inductors (IVVR) combined with novel advanced dielectric materials to drastically reduce physical footprint without scaling up DCR or magnetic core hysteresis losses.

• Predictive Energy Management Algorithms: Implement ultra-lightweight digital control logic at the edge utilizing marginal predictive models to adapt switching frequencies (PFM) and duty cycles based on historical energy harvesting patterns.

• Process, Voltage, and Temperature (PVT) Aging Mitigation: Optimize digital cold-start self-calibration loops to operate adaptively against thermal wear and long-term physical silicon degradation, maintaining sub-threshold reference stability without penalizing the nano-watt power budget.

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