PART 6: SEMICONDUCTOR MANUFACTURING From fabs to the markets: the packaged chips

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The common black packaging of the semiconductors gave rise to the word “chips” as a synonym. Packaging is the final procedure of microfabrication that takes an IC from fabs to the inventories/markets. The final/sixth article in the semiconductor manufacturing series discusses the packaging process and lists various types of IC packages.

A brief overview of IC packaging

Packaging or assembly is among the final backend procedures of the microfabrication process, beyond which the die is converted into a commercial product. Semiconductors are packaged to prevent mechanical damage, and corrosion, dissipate heat, promote efficient connections, and high-speed signal transmission, ease assembly procedures, and make an IC identifiable.

Wafers are cut into multiple dies and put in a protective case. The case is bonded with wires, molded, and plated. Pins come out of the case for effective electrical connections to other components, wires, or a PCB. The process of putting semiconductors in small cases is known as packaging.

These protective cases, usually black in color, are made from metal, plastic, or ceramic materials. Packages are designated and registered with worldwide acceptance. Apart from directly affecting the functionality, application, and speed, the packaging process defines the manufacturer and the vendor.

Each package has well-defined dimensions for pin size, distance between pins, hole diameter, pads, and various other important parameters. A typical IC is imprinted with the manufacturer's name, logic device number, date, location code, part number, etc.

The IC on the left can be interpreted as follows:

• “NE” is the manufacturer’s name- Signetics.

• 555 is the series number, indicating the timer IC.

• 78 is the year of manufacture- 1978.

• 28 is the ISO week or the 28th week of the same year (1978).

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The assembly process

Packaging or assembly is among the final backend procedures of the microfabrication. ICs are tested multiple times at various stages. The processes involved in electrical die sorting initiate the early packaging procedures. The section lists the steps involved in packaging semiconductor devices.

There are four levels of semiconductor packaging:

IC Packaging Level 0: Wafer sawing process cuts the wafer into dies. The microfabrication testing: electrical die sorting article in the semiconductor manufacturing series discusses this process.

IC Packaging Level 1: Chip-level packaging.

1. Die attach

Die attach is an assembly technique for converting an unprotected or uncovered die into a packaged semiconductor device. The die is placed on the substrate which might be a leadframe or a laminate substrate. Depending on the application, the die is bonded to the substrate through adhesive epoxy or soft solder methods. The die is placed on a central pad in a leadframe structure, a base for mounting the die on a board.

2. Laser marking

Inking or marking means labeling the tested chips during the test with a “zero” or “one” through lasers. The reliable die marked with “1” is called a “Known Good Die”. On the other hand, the faulty die with a “0” marking is called a “Bad Die”. KGD, the functional chips, are tested, and packaged. BD is not rejected but sent into a failure analysis lab to cut down on the costs.

3. Wire bonding

Wire bond enables connecting multiple I/O terminals to individual pins that come out of the package. Gold and silver bonds, two excellent conductors of electricity, were earlier a great option in IC packaging. However, gold and silver are extremely costly to increase overall expenses. Copper ball bonding is another good option but is at risk of corrosion. Aluminum wire bonding is popular in power devices, owing to their large diameter.

IC Packaging Level 2: Die is mounted on the surface of the card (leadframe).

4. Molding

Without a protective cover, an IC is at risk of mechanical, chemical, and electrical damage. Molding is the process of encapsulating the device and protecting it from environmental damage. In layman's terms, an IC is put inside a cover. The top, side, and bottom of the IC are molded as per the application and manufacturer’s protocols. The molding material is an epoxy molding resin containing inorganic catalysts, stress modifiers, and adhesion promoters.

IC Packaging Level 3: Card connection to the board.

5. Tin plating and singulation

Tin plating is among the last packaging procedures. The process offers corrosion resistance, thermal performance, and reliability of soldered joints as the tin-plated layer acts as a protective layer. Furthermore, the last step in IC packaging is singulation. The process of singulation means separating the IC from the leadframe or the substrate and making it a stand-alone device. The “singulated” device is tested for functionality and sent to inventories/markets.

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IC packages

Moore’s law is constantly pressuring chip makers to reduce IC sizes over the span of every two years. It gives rise to new packaging technologies and enhanced benefits. The table below lists some popular IC packages in use.

DIP (Dual in-line package)

DIP is a THT (Through-hole technology) common among engineering students and beginners. Pins are spaced at 2.54 mm. DIP IC is made either from plastic or ceramic and supports a pin count of 4, 8, 14, 18, 20, 28, and 40.

SIP (Single in-line package)

SIP is a THT for power devices such as power amplifiers. SIP IC supports a maximum pin count of 64 and a minimum pin count of 24. The package often uses a heat sink for power dissipation.

QIP (Quad in-line package)

QIP is a THT similar to DIP but its leads are bent in a zig-zag pattern. Some chipmakers have also developed leadless QIP ICs. The QIP IC often uses heat sink tabs in power applications.

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SOIC (Small outline integrated circuit)

A SOIC is an SMD (Surface mount device), smaller and narrower than DIP THT packages. Pins are spaced at 1.27 mm. A SOIC can have a minimum pin count of 8 and a maximum pin count of 48.

QFP (Quad flat package)

QFP is a flat package technology for producing high pin count ICs. Pins are spaced at either 0.5 mm, 0.65 mm, or 0.8 mm. QFP IC supports a minimum pin count of 32 and a maximum pin count as high as 200.

LGA (Land grid array)

LGA packages are modern IC packages in which pins are not placed on the IC. Instead, the pins are mounted on the sockets.

Ball (Ball grid array)

Not to be confused with LGA packages, BGA packaging is widely used in microprocessors. BGA packaging permanently mounts components on a microprocessor to eliminate complex circuitry and reduce the project size.

Small outline transistor (SOT)

Diodes, transistors, and voltage regulators are packaged in SOT packages. SOT-XXX has numerous types like SOT-23, SOT-323, SOT-28, and SOT-416.

TO (Transistor Outline)

TO-XX is a popular packaging series for transistors and diodes. One of the popular TO-92 transistor packages is alternatively called the SOT-54 package.

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Conclusion

The final article of the semiconductor manufacturing series concludes with the assembly process and lists different types of packages. Once assembled, ICs are tested again for functionality. Post testing and packaging processes, an IC is loaded into the supply chain.

"Semiconductor Manufacturing" article series

• Part 1: Introduction to semiconductor manufacturing

• Part 2: The Semiconductor “Wafers”

• Part 3: Semiconductor circuit design: key chemical procedures

• Part 4: Doping: The semiconductive character

• Part 5: Microfabrication testing: Electrical die sorting (EDS)

• Part 6: From fabs to the markets: the packaged chips

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