sponsoredCOOLING SOLUTIONS Maximize Lifetime & Power Density in High Power Semiconductors Modules

Sponsored by

Littelfuse Europe GmbH

Power electronics must achieve higher power in smaller housings, boosting efficiency and reducing costs. SiC-MOSFETs can replace IGBTs but are pricier. Press pack-device approaches and active heat sinks can enhance IGBT designs, improving performance.

Comparing power modules and disc-style devices

The trend of increasing power density in power semiconductors is approaching physical limitations due to isolation requirements. To overcome these limitations, efficient heat extraction methods are essential. Direct liquid cooling combined with advanced chip and interconnection technology offers a promising solution. Shifting from classical isolated assemblies to non-isolated counterparts can increase power density by a factor of 10.

Higher power density results in increased losses per area and elevated temperatures, stressing interconnecting joints. This necessitates replacing soft-soldered connections with sintering for enhanced stability and longevity. Improved cooling is critical, as insulating DCB ceramics limit thermal transfer.

High-power disc devices, unlike power semiconductor modules, utilize electrically active cold plates for efficient cooling and material savings. Figure 1 depicts a typical power semiconductor module, while Figure 2 shows a stack assembly of a 2400 A / 4500 V 3-level phase-leg with active aluminum cold plates, which also serve as terminals and snubber circuit connection points. Efficient thermal management is achieved using non-conducting cooling liquids, such as a deionized water-glycol mixture.

Feasibility Study

To enhance the thermal resistance by eliminating the direct copper bond (DCB) ceramics, 1200 V/200 A IGBT dies were directly soldered to a liquid-cooled plate. The initial approach utilized bond wires to connect components, leading to the first device under test (DUT), as shown in Figure 3. This 200 A IGBT die employed eight bond wires, each capable of handling 25 A, to link the emitters to the power terminals.

The DUT underwent testing with an infrared (IR) imaging setup, starting at 50 A and increasing in 50 A increments. At 200 A, the chip temperature rose by 70K, while the bond wires exceeded 400°C, as depicted in Figure 5. At 250 A, the bond wires fused, highlighting the limitations of this approach. Consequently, a new design was developed that used clip-soldered connections instead of bond wires, facilitated by a new solderable chip-metallization, as illustrated in Figure 6.

This new design showed significant improvement: at 200 A, the chip temperature reached 94°C, similar to the previous bond wire design. The clip's maximum temperature was 78°C, far below the bond wires' 400°C, as seen in Figure 7. The new design could handle currents exceeding 275 A before reaching an operating temperature of T_vj = 150°C.

An analysis of power loss density indicated that the setup could handle up to 380 W/cm² at a temperature differential of 100 K, allowing a maximum current of 450 A for the new chip with a 2 cm² area, and up to 250 A for the 150 A/183 mm² standard die. These results reflect a marked improvement in thermal management and operational efficiency with the new design.

Electric testing

Though the main focus was thermal performance, electrical behaviour was tested. The double-pulse-test summarized in Figure 8 revealed sufficiently clean switching. Despite the non-optimized layout, the results were good enough for potential series development.

Cyclic load testing

Power electronic components' lifetime is enhanced by outstanding thermal performance. As defined in IEC 60749, a power cycling test, or PC_sec, was performed on the pad-and-clip assembly, which is expected to surpass bond-wire systems due to the elimination of bond-lift-off and bond-heel-crack issues. The test subjected several devices to these conditions, and despite the IGBT being rated at 150 A but burdened 250 A, the chips, in a single arrangement, lasted approximately 145,000 cycles before reaching a 5 % forward voltage increase as depicted in Figure 9. This performance is significantly better compared to 80,000 cycles for solder-bond technology, indicating potential for further improvements in chip metallization and solder alloys.

Conclusion

The omnipresent trend of increasing power density in power semiconductors as they are built today starts reaching physical limits due to the isolation requirement. To push these limits further, new methods to extract heat from power semiconductors more efficiently need to be identified.

One way of doing so is direct liquid cooling combined with a suitable chip- and interconnection technology as presented.

The shift from classical isolated assemblies to non-isolated counterparts opens the door to increase power density by a factor of 10, compared to today’s options.

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