CHIP INDUSTRY NEWS Chip industry update: A review of Q3 2025

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As the chip shortage subsides for most industries, the constraint has shifted to advanced AI components like high-end GPUs and CoWoS packaging. Meanwhile, geopolitical tensions, especially between the U.S. and China, are exacerbating supply chain complexities, pushing some towards domestic Chinese solutions.

By mid-2025, the world that was turned upside down by the COVID-era chip shortage has largely settled back into a predictable rhythm. For automotive, industrial, and embedded customers, Q3 and 2025 on the whole marked the end of abnormality: lead times compressed, safety stock started to flow again, and design teams could finally focus on product transitions rather than procurement triage.

MCUs, power analog, sensors, and display drivers — the poster children of the 2021–2022 shortages — are no longer in crisis mode. NXP and Microchip both reported sequential revenue declines in their industrial segments in Q2 and Q3, citing customer inventory digesti ive NVL72 rack-scale servers, became the flagship example of this problem in Q3. Despite TSMC’s mature 5nm yield, the real constraint is in the backend. Specifically, CoWoS-L (Chip-on-Wafer-on-Substrate with Large Interposer) packaging capacity continues to be the long pole in the tent. Unlike earlier CoWoS-S packaging, which stacks HBM atop the GPU die with more forgiving substrates, CoWoS-L requires larger interposers and tighter substrate tolerances to connect GPUs to multiple HBM stacks at scale. These substrates remain scarce, and the final assembly capacity isn’t easily expanded.

TSMC confirmed this in its Q2 earnings call, noting that while wafer output is strong, CoWoS assembly is capacity-constrained through at least the first half of 2026. The company has accelerated expansion plans, but demand is growing faster than supply, especially as multiple hyperscalers race to deploy tens of thousands of AI accelerators per quarter.

And it’s not just the package. The memory next to the die — HBM3, HBM3e, and soon HBM4 — is also heavily oversubscribed. SK hynix, the dominant HBM supplier, said in August that its 2024 allocation was fully booked and that “2025 is almost sold out.” The company has completed internal HBM4 validation and is preparing production, but meaningful volume isn’t expected until late 2026.

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That memory constraint is dragging on every AI server bill of materials. A Blackwell GPU without HBM is incomplete, and customers can’t procure modules in pieces. The result is tight availability, secondary-market premiums, and long visibility gaps in hyperscale deployment planning.

And the pain is spreading. As SK hynix and Samsung reallocate DRAM fab lines and packaging capacity toward high-margin HBM, standard DDR4 and DDR5 availability has tightened. NAND and DRAM prices surged by up to 20 % Q3, with further hikes expected in Q4, particularly in DDR4, where fewer vendors are manufacturing new stock. Meanwhile, NAND contract pricing is also climbing, as enterprise SSD demand surges to feed training clusters. Analysts expect 5–10 % increases in the final quarter of 2025.

Geopolitics adds fuel to the fire

The physical limits of packaging and memory are only part of the picture. Geopolitics — particularly U.S.-China tensions over AI hardware — continued to distort the supply landscape in Q3.

At the start of 2025, new U.S. export controls restricted Nvidia’s ability to sell high-performance AI GPUs into China without special licenses. Nvidia responded by designing the H20, a modified GPU with reduced compute and interconnect specs, tailored to meet the thresholds. That chip began shipping in limited quantities under license, but Beijing’s reaction wasn’t enthusiastic.

In July, Chinese regulators and state media pushed back, questioning the value of the compromised designs and floating antitrust concerns against Nvidia itself. This introduced even more uncertainty into demand planning. Chinese hyperscalers paused or canceled some orders, concerned that any newly acquired chips could become obsolete or sanctioned mid-lifecycle. Nvidia’s RTX6000D, another “China-compliant” product, was already seeing muted interest due to comparisons with banned but grey-market-accessible alternatives like the RTX 5090.

The result is that customers in China are increasingly shifting to domestic accelerators from Huawei, Biren, and Alibaba’s T-Head, even when those come with software and tooling friction. For global engineering teams, this bifurcation creates real risk. Systems must now be built around either U.S.-compliant Nvidia chips or domestic Chinese solutions, with diverging firmware, compilers, and software stacks. That increases engineering overhead, slows time-to-deployment, and makes global supply planning harder.

The new rules of chip supply

Recent events have made one thing painfully clear: wafer starts alone no longer guarantee delivery. For advanced AI silicon, the real gating factors are the availability of CoWoS packaging slots and high-bandwidth memory allocations. Engineering teams now need to think in terms of complete modules, not just die availability. A GPU without its HBM stacks and package isn't a product; it's an incomplete component stuck in the pipeline.

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At the same time, policy risk has become a fixed constraint in design. For any system destined for, or even adjacent to, China, dual-bill-of-material strategies are not optional. Designers must support both U.S.-compliant Nvidia SKUs and domestic Chinese accelerators, each with their own firmware, software stack, and validation pathway. Every policy shift, every export rule, every regulatory rumor now lands with real, architectural consequences.

Even below the AI stack, memory pricing is quietly reshaping system design decisions. The cost of DDR4 and DDR5 has risen sharply, not because of direct scarcity, but because DRAM vendors are pivoting capacity toward premium HBM production. That shift is driving up prices for what used to be commodity memory. NAND is seeing a similar squeeze as hyperscalers race to feed high-capacity storage clusters. The result is that total system costs are in flux, and power budgets tied to different DIMM and SSD choices may shift. Design teams must build in pricing tolerance and leave room for reconfiguration.

And while the market celebrates AI’s ascent, engineers can’t afford to ignore what’s slipping through the cracks. As fabs chase higher-margin wafers, legacy nodes and older memory standards — DDR4, LPDDR4X, eMMC — are quietly aging out. Foundries are hinting at end-of-life timelines, and supply is already tightening. For products still tied to those platforms, the window to secure last-time buys and second-source validation is closing fast.

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