PCIM 2026 - YOUNG ENGINEER AWARD
Shared DC-Link Optimization for Paralleled Inverters Using Phase- Shifted PWM
This paper presents a novel optimization methodology for shared DC-link (SDCL) architectures in paralleled inverters, utilizing phase-shifted carrier PWM as well as a fast MATLAB-based current reconstruction method.
In combination with 2-level and 3-level T-Type NPC inverter topologies, a shared DC-link RMS current reduction of up to 50% is achieved. Insights in the modeling approach as well as electrical and weight-optimization results, validated against PLECS simulations, are presented. The methodology enables further innovation due to significant capacitor weight savings in applications such as more electric aircraft, aerospace propulsion systems, multiphase electric drives, and high-power industrial systems. This paper showcases its capabilities for a 12-phase asymmetrical PMSM propulsion system with combined 2L and 3L-TNPC inverter configurations.
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